71. G. S. Lin and J. B. Kuo, “Fringing-Created Thin-Channel-Impact (FINCE) Related Capacitance Conclusion away from Nanometer FD SOI NMOS Gizmos Playing with Mesa-Separation Thru 3d Simulator” , EDSM , Taiwan ,

72. J. B. Kuo, “Progression out of Bootstrap Techniques in Reasonable-Voltage CMOS Electronic VLSI Circuits to possess SOC Programs” , IWSOC , Banff, Canada ,

P. Yang, “Entrance Misalignment Effect Relevant Capacitance Decisions from an effective 100nm DG FD SOI NMOS Device that have n+/p+ Poly Better/Base Door” , ICSICT , Beijing, China

73. Grams. Y. Liu, Letter. C. Wang and you can J. B. Kuo, “Energy-Successful CMOS Highest-Load Rider Routine on Complementary Adiabatic/Bootstrap (CAB) Technique for Lowest-Strength TFT-Liquid crystal display System Applications” , ISCAS , Kobe, Japan ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Technology regarding 100nm FD SOI CMOS Equipment that have HfO2 High-k Entrance Dielectric Considering Straight and Fringing Displacement Consequences” , HKEDSSC , Hong kong ,

75. J. B. KUo, C. H. Hsu and you will C. P. Yang, “Gate-Misalignment Relevant Capacitance Conclusion out of good 100nm DG SOI MOS Equipment having Marin female N+/p+ Top/Base Entrance” , HKEDSSC , Hong kong ,

76. G. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Effective CMOS Higher-Weight Rider Routine to the Subservient Adiabatic/Bootstrap (CAB) Way of Reasonable-Strength TFT-Liquid crystal display Program Applications” , ISCAS , Kobe, Japan ,

77. H. P. Chen and you can J. B. Kuo, “An excellent 0.8V CMOS TSPC Adiabatic DCVS Reason Routine to the Bootstrap Techniques for Reasonable-Strength VLSI” , ICECS , Israel ,

B. Kuo, “A book 0

80. J. B. Kuo and H. P. Chen, “A decreased-Current CMOS Stream Rider towards the Adiabatic and you will Bootstrap Tricks for Low-Electricity Program Programs” , MWSCAS , Hiroshima, The japanese ,

83. Meters. T. Lin, E. C. Sun, and you can J. B. Kuo, “Asymmetric Gate Misalignment Influence on Subthreshold Features DG SOI NMOS Gadgets Given Fringing Electric Field effect” , Electron Devices and you can Question Symposium ,

84. J. B. Kuo, Age. C. Sunlight, and you will M. T. Lin, “Studies regarding Entrance Misalignment Effect on this new Tolerance Voltage from Twice-Door (DG) Ultrathin FD SOI NMOS Devices Having fun with a concise Design Given Fringing Electric Field effect” , IEEE Electron Gizmos having Microwave oven and you may Optoelectronic Programs ,

86. Age. Shen and you may J. 8V BP-DTMOS Stuff Addressable Memories Telephone Circuit Produced from SOI-DTMOS Processes” , IEEE Meeting on Electron Equipment and Solid state Circuits , Hong-kong ,

87. P. C. Chen and you may J. B. Kuo, “ic Reason Circuit Playing with a primary Bootstrap (DB) Technique for Low-voltage CMOS VLSI” , In the world Symposium into Circuits and you will Assistance ,

89. J. B. Kuo and you will S. C. Lin, “Compact Malfunction Model having PD SOI NMOS Gizmos Considering BJT/MOS Impression Ionization having Spice Circuits Simulation” , IEDMS , Taipei ,

ninety. J. B. Kuo and S. C. Lin, “Lightweight LDD/FD SOI CMOS Unit Design Offered Opportunity Transport and you may Notice Heat for Spruce Circuit Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you can J. B. Kuo, “Fringing-Induced Barrier Lowering (FIBL) Ramifications of 100nm FD SOI NMOS Gadgets with a high Permittivity Entrance Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Meeting Proc , Williamsburg ,

92. J. B. Kuo and S. C. Lin, “The brand new Fringing Digital Field-effect on the Small-Route Impression Threshold Voltage out of FD SOI NMOS Gizmos with LDD/Sidewall Oxide Spacer Framework” , Hong kong Electron Equipment Fulfilling ,

93. C. L. Yang and you may J. B. Kuo, “High-Temperature Quasi-Saturation Brand of Highest-Voltage DMOS Energy Devices” , Hong kong Electron Gizmos Meeting ,

94. E. Shen and you may J. B. Kuo, “0.8V CMOS Stuff-Addressable-Thoughts (CAM) Mobile Ciurcuit which have an easy Level-Compare Abilities Having fun with Majority PMOS Dynamic-Threshold (BP-DTMOS) Method According to Simple CMOS Tech to have Reasonable-Voltage VLSI Systems” , Global Symposium towards the Circuits and Assistance (ISCAS) Proceedings , Arizona ,